This application claims the benefit of Korean Patent Application No. 98-36934, filed Sep. 8, 1998, the disclosure of which is hereby incorporated herein by reference.
The present invention relates generally to the field of integrated circuit testing, and, more particularly, to systems for testing integrated circuit memory modules and devices.
Improvements in both speed and functionality of central processing units (CPUs) have generally resulted in accompanying improvements in memory devices to support the operation of these improved CPUs. These memory devices may comprise a plurality of integrated circuit memory elements. That is, a single memory module may include a plurality of conventional or xe2x80x9cnormalxe2x80x9d memory elements. Unfortunately, the fabrication process may damage one or more of the conventional memory elements that comprise the memory module. Therefore, it may be desirable to test the various memory elements within a memory module to identify any elements that are inoperable.
FIG. 1 is a high-level block diagram that depicts a conventional testing system for verifying the operation of a memory module. A test unit 100 includes both the hardware and software for controlling the testing operation. The test unit 100 interfaces with a load board 120 that is used for transmitting signals output from the test unit 100. A socket printed circuit board 140 and socket 160 are used to interface the load board 120 to a memory module 180.
Broadly stated, the test unit 100 is used to test the memory module 180 as follows: The test unit 100 provides a read instruction and/or a write instruction to one or more memory elements within the memory module 180 through the load board 120, printed circuit board 140, and socket 160. The test unit 100 can then determine whether a particular memory element within the memory module 180 is operating properly by comparing data written into a memory cell with data read from the memory cell to determine if they are identical.
FIG. 2 is a schematic of a conventional test configuration using independent channel signaling that illustrates the test unit 100, load board 120, and memory module 180 in more detail. The test unit 100 includes a plurality of data input drivers 12-1, 12-3, . . . , and 12-(2n-1) that receive control signals and address data through the input terminals 10-1, 10-5, . . . , and 10-(4n-3). The test unit 100 further includes a plurality of data input drivers 12-2, 12-4, . . . , and 12-2n that receive write data through the input terminals 10-2, 10-6, . . . , and 10-(4n-2). Finally, the test unit 100 includes a plurality of comparators 14-1, 14-2, . . . , and 14-n that are used to compare read data from the memory module 180 with expected data provided through the input terminals 10-4, 10-8, . . . , and 10-4n and to generate a comparison result at the output terminals 10-3, 10-7, and 10-(4n-1).
The load board 120 includes a plurality of transmission lines 20-1, 20-3, . . . , and 20-(2n-1) that are connected to the output terminals of the data input drivers 12-1, 12-3, . . . , and 12-(2n-1). In addition, the load board 120 includes a plurality of transmission lines 20-2, 20-4, . . . , and 20-2n that are connected to the output terminals of the data input drivers 12-2, 12-4, . . . , and 12-2n and one of the input terminals of the comparators 14-1, 14-2, . . . , and 14-n as illustrated.
The memory module 180 includes a plurality of memory devices or elements 32-1, 32-2, . . . , and 32-n that include input pins 30-1, 30-3, . . . , and 30-(2n-1) and input/output pins 30-2, 30-4, . . . , and 30-2n. The input pins 30-1, 30-3, . . . , and 30-(2n-1) are connected to the transmission lines 20-1, 20-3, . . . , and 20-(2n-1) and the input/output pins 30-2, 30-4, . . . , and 30-2n are connected to the transmission lines 202, 20-4, . . . , and 20-2n. For purposes of illustration, the memory devices 32-1, 32-2, . . . , and 32-n are each depicted with a single input pin and a single input/output pin. It is nevertheless understood to those skilled in the art that the memory devices 32-1, 32-2, . . . , and 32-n typically include both a plurality of input pins and input/output pins.
A method that may be used for testing the memory module 180 is described hereafter. A typical test cycle involves the following steps: 1) input the write instruction and the write address, 2) perform a data write operation, 3) input the read instruction and read address, and 4) perform a data read operation. This cycle may be repeatedly performed until the operability of all memory devices 32-1, 32-2, . . . , and 32-n in the memory module 180 is verified. This test cycle will be discussed hereafter with reference to the independent channel test configuration of FIG. 2.
The test unit 100 receives the write instruction and write address through the input terminals 10-1, 10-5, . . . , and 10-(4n-3). The write instruction and write address are then provided to the input pins 30-1, 30-3, . . . , and 30-(2n-1) of the memory devices 32-1, 32-2, . . . , and 32-n through the data input drivers 12-1, 12-3, . . . , and 12(2n-1) and the transmission lines 20-1, 20-3, . . . , and 20-(2n-1). Next, the memory devices 32-1, 32-2, . . . , and 32-n prepare for the write operation.
The data to be written into the selected memory cell is received through the input terminals 10-2, 10-6, . . . , and 10-(4n-2) and is provided to the input/output pins 30-2, 30-4, . . . , and 30-2n of the memory devices 32-1, 32-2, . . . , and 32-n through the data input drivers 12-2, 12-4, . . . , and 12-2n and the transmission lines 20-2, 20-4, . . . , and 20-2n. The memory devices 32-1, 32-2, . . . , and 32-n then enable the data to be written into the selected memory cell.
After completing the data write operation, the test unit 100 receives the read instruction and read address through the input terminals 10-1, 10-5, . . . , and 10-(4n-3) and, simultaneously, the data that has been previously written into the memory cell corresponding to the read address is received at the input terminals 10-4, 10-8, . . . , and 10-4n. The read instruction and read address are provided to the input pins 30-1, 30-3, . . . , and 30-(2n-1) of the memory devices 32-1, 32-2, . . . , and 32-n through the data input drivers 12-1, 12-3, . . . , and 12-(2n-1) and the transmission lines 20-1, 20-3, . . . , and 20-(2n-1). Next, the memory devices 32-1, 32-2, . . . , and 32-n prepare for the read operation.
The data are then read through the input/output pins 30-2, 30-4, . . . , and 30-2n and transmission lines 20-2, 20-4, . . . , and 20-2n traversing the same path that was used to write data to the memory devices 32-1, 32-2, . . . , and 32-n. The data that are read from the memory devices 32-1, 32-2, . . . , and 32-n are compared by the comparators 14-1, 14-2, . . . , and 14-n with the expected data provided at the input terminals 10-4, 10-8, . . . , and 10-4n. The results of the comparison are provided through the output terminals 10-3, 10-7, and 10-(4n-1).
The test unit 100 uses the results of the comparison operation to determine whether the memory devices 32-1, 32-2, . . . , and 32-n are operating properly. More specifically, if a comparison result indicates that the read data and the expected data are identical, then the test unit 100 concludes that a particular memory device 32-1, 32-2, . . . , and 32-n is operating properly. On the other hand, if a comparison result indicates that the read data and expected data are not identical, then the test unit 100 identifies the particular memory device 32-1, 32-2, . . . , and 32-n as being inoperable or damaged.
Because each memory device 32-1, 32-2, . . . , and 32-n is accessed through independent signaling channels (i.e., transmission lines 20-1, 20-3, . . . , and 20-(2n-1) and transmission lines 20-2, 20-4, . . . , and 20-2n), all of the memory devices 32-1, 32-2, . . . , and 32-n contained in the memory module 180 can be tested simultaneously. Note that if the memory devices 32-1, 32-2, . . . , and 32-n that comprise the memory module 180 operate at a relatively low speed, then the testing method described in the foregoing may not be affected by the round trip delay of signals between the test unit 100 and the memory module 180. If, however, the memory devices 32-1, 32-2, . . . , and 32-n that comprise the memory module 180 operate at a relatively high speed, then the memory devices 32-1, 32-2, . . . , and 32-n may transition rapidly from a read mode to a write mode, which can cause the read and the write operations to interfere with each other unless the testing procedure accounts for the round trip delay of signals between the test unit 100 and the memory module 180.
Furthermore, if the memory devices 32-1, 32-2, . . . , and 32-n that comprise the memory module 180 operate at a relatively low speed, then the signals transferred between the memory module 180 and the test unit 100 and/or load board 120 are typically unaffected by impedance mismatches between the components. If, however, the memory devices 32-1, 32-2, . . . , and 32-n that comprise the memory module 180 operate at a relatively high speed, then impedance mismatches between the memory module 180 and the test unit 100 and/or load board 120 may cause signal distortion. Typically, the impedances of the test unit 100 and the load board 120 are predetermined or adjusted to match so as to reduce distortion in signals transferred therebetween. Nevertheless, the impedances of the test unit 100 and/or the load board 120 may be different than the impedances of the memory module 180 and/or the transmission lines (i.e., transmission lines 20-1, 20-3, . . . , and 20-(2n-1) and transmission lines 20-2, 20-4, . . . , and 20-2n), which can result in signal distortion, especially when the memory devices 32-1, 32-2, . . . , and 32-n operate at a relatively high speed.
Thus, in summary, the conventional test configuration of FIG. 2 may be useful for testing memory devices that operate at a relatively low speed. When testing memory devices that operate at a relatively high speed, however, the test configuration may be adversely affected by round trip signal delays and signal distortion due to impedance mismatches as discussed hereinabove.
FIG. 3 is a schematic of a conventional test configuration that uses common channel signaling. The test unit 100 includes a data input driver 12-1 that receives control signals and address data through an input terminal 10-1. The test unit 100 further includes a data input driver 12-2 that receives write data through an input terminal 10-2. Finally, the test unit 100 includes a comparator 14 that is used to compare read data from the memory module 180 with expected data provided through an input terminal 10-4 and to generate a comparison result at the output terminal 10-3.
The load board 120 includes a transmission line 20-1 that is connected to the output terminal of the data input driver 12-1. In addition, the load board 120 includes a transmission line 20-2 that is connected to the output terminal of the data input driver 12-2 and one of the input terminals of the comparator 14 as illustrated.
The memory module 180 includes a plurality of memory devices or elements 32-1, 32-2, . . . , and 32-n that include input pins 30-1, 30-3, . . . , and 30-(2n-1) and input/output pins 30-2, 30-4, . . . , and 30-2n. The input pins 30-1, 30-3, . . . , and 30-(2n-1) are connected to the transmission line 20-1 and the input/output pins 30-2, 30-4, . . . , and 30-2n are connected to the transmission line 20-2. For purposes of illustration, the memory devices 32-1, 32-2, . . . , and 32-n are each depicted with a single input pin and a single input/output pin. It is nevertheless understood to those skilled in the art that the memory devices 32-1, 32-2, . . . , and 32-n typically include both a plurality of input pins and input/output pins. Moreover, the input pins 30-1, 30-3, . . . , and 30-(2n-1) for all of the memory devices 32-1, 32-2, . . . , and 32-n are shown connected to a single channel (i.e., transmission line 20-1) and the input/output pins 30-2, 30-4, . . . , and 30-2n for all of the memory devices 32-1, 32-2, . . . , and 32-n are shown connected to a single channel (i.e., transmission line 20-2). Alternatively, it should be understood that the memory devices 32-1, 32-2, . . . , and 32-n could be divided into groups of n units such that all n units in a single group are connected via common channels while memory devices in separate groups remain independent. As illustrated in FIG. 3, because the input pins 30-1, 30-3, . . . , and 30-(2n-1) of the memory devices 32-1, 32-2, . . . , and 32-n are commonly connected to a single data input driver 12-1 and the input/output pins 30-2, 30-4, . . . , and 30-2n of the memory devices 32-1, 32-2, . . . , and 32-n are connected to a single data input driver 12-2, the memory devices 32-1, 32-2, . . . , and 32-n cannot be tested in parallel, but instead are tested serially.
Although the test configuration of FIG. 3 may be different than that of FIG. 2, it nevertheless may suffer from the same disadvantages. That is, the test configuration of FIG. 3 may be adversely affected by round trip signal delays and signal distortion due to impedance mismatches when testing memory devices that operate at a relatively high speed.
It is therefore an object of the present invention to provide improved test systems for testing integrated circuit memory modules and devices.
It is another object of the present invention to provide improved test systems that can be used for testing high-speed integrated circuit memory modules and devices.
It is yet another object of the present invention to provide improved test systems for testing integrated circuit memory modules and devices that can reduce signal distortion that may occur as signals are passed between a test system and a memory module or device under test.
These and other objects, advantages, and features of the present invention may be provided by integrated circuit test systems that include a first input driver having an output terminal that is connected to a first test system port and a first biasing device that is connected between the first test system port and a reference voltage. The first biasing device comprises a Thxc3xa9venin equivalent circuit that is represented by an impedance element and a non-zero power source. The impedance element may be used to match the impedance of a device under test, which can reduce distortion in signals passed between the device under test and the test system. Furthermore, the power source may be used to provide direct current (DC) signals at the pins of the device under test, which can allow the swing height (e.g., amplitude or magnitude) of the test signals to be reduced. That is, the test signals are superimposed upon the DC voltages to allow xe2x80x9chighxe2x80x9d and xe2x80x9clowxe2x80x9d logic levels to be manifested via relatively minor swings in the test signals. By reducing the swing height of the test signals, transmission speed can be improved thereby reducing round trip signal delay.
In accordance with an aspect of the invention, a second input driver has an output terminal that is connected to a second test system port and a second biasing device is connected between the second test system port and a reference voltage. The second biasing device comprising a Thxc3xa9venin equivalent circuit that is represented by an impedance element and a non-zero power source.
In accordance with another aspect of the invention, a third input driver has an output terminal that is connected to the first test system port and a fourth input driver has an output terminal that is connected to the second test system port.
In accordance with still another aspect of the present invention, first and second transmission lines are used to connect the first and third input drivers to the first test system port and third and fourth transmission lines are used to connect the second and fourth input drivers to the second test system port.
In accordance with yet another aspect of the present invention, one of the first and third input drivers generates a DC signal when the other input driver in the pair transmits a control signal, e.g., an instruction and/or address signal.
In accordance with still another aspect of the present invention, the second and fourth input drivers both generate a DC signal when data is read from the memory device through the second test system port.
In accordance with still another aspect of the present invention, one of the second and fourth input drivers generates a DC signal when the other input driver in the pair transmits write data.
The DC signals generated by the input drivers are used conjunction with the DC signals provided by the power sources to ensure that a desired DC offset voltage is maintained on the signal transmission paths.
Test systems in accordance with the present invention can also be used to test a memory module having a plurality of memory devices with each device having an input pin and an input/output pin. In accordance with an illustrative embodiment, a test system includes a first signal channel that connects the input pins of the plurality of memory devices to each other and a second signal channel that connects the input/output pins of the plurality of memory devices to each other. A first pair of input drivers is connected to the first signal channel and a second pair of input drivers is connected to the second signal channel. In addition, a first impedance element and first power source are connected in series between the first signal channel and ground and a second impedance element and second power source are connected in series between the second signal channel and ground.
In accordance with yet another illustrative embodiment of the present invention, a test system for a memory module includes a first signal channel that connects the input pins of a plurality of memory devices to each other and a second signal channel that connects the input/output pins of the plurality of memory devices to each other. First and second input drivers are connected to the first signal channel at first and second nodes respectively. Similarly, third and fourth input drivers are connected to the second signal channel at first and second nodes respectively. In addition, a first impedance element and first power source are connected in series between first node of the first signal channel and ground, a second impedance element and second power source are connected in series between the second node of the first signal channel and ground, a third impedance element and third power source are connected in series between the first node of the second signal channel and ground, and a fourth impedance element and a fourth power source are connected in series between the second node of the second signal channel and ground.
The test systems according to the present invention, which include impedance elements and power sources for maintaining a DC signal on the test signal transmission paths, can thus be used to test high-speed memory devices where signal distortion and round trip signal delay may be problematic.